This section deals with the existing literatures related to analog circuit optimization. It outlines a summary of all the resource materials, authorial credentials, content credibility, source credibility, text credibility- Fluid integration of the source evaluation. A true literature review gives the proper sense of works that technology has achieved till date into that specified topic which helps one researcher to bring down his own research problem.
Han Young et al. (1990) developed an analog silicon compilation system for CMOS op amps (OPASYN). The synthesis starts from a certain specification. From its database, program selects op amp topology that suits most with the given specification. Using parametric optimization the circuit then determines optimal value for its parameters. It also produces Design-Rule-Correct compact layout of the optimized op amp.
Yang et al. (1995) proposed a Simulated Annealing (SA) algorithm for topology selection and sizing. In analog cells, topology choice and sizing simultaneously is efficient than normal two step mode synthesis. Basic problem with that approach is that super circuits must be worked out for each sort of analog cells.
Chen et al. (2000) placed an iterative optimization idea for improving delay in digital circuit. Instead of only adjusting that gate sizes to reduce delay, they adjusted wire loads of the gates by repositioning them using geometric program. It gave better result in deep sub-micron design where the effect of interconnect delays dominates
Mandal P and Visvanathan V (2001) devised an efficient technique for sizing of op amp by sequential convex optimization problem. This method then prototyped in MATLAB to apply into CMOS two stage op amp.